Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
September 14, 2010
Patent Application Number
11710940
Date Filed
February 27, 2007
Patent Primary Examiner
Patent abstract
A test mode enable circuit for putting a device in a test mode includes a serial-to-parallel shift register reset by a reset signal, a decoder circuit, and a gate circuit. The shift register receives and converts a control signal in serial form to control data in parallel form. The decoder circuit receives and decodes the control data to a test mode enable signal that puts the device in the test mode. The decoder circuit outputs the test mode enable signal to the gate circuit only when the control data matches a predetermined key pattern. The gate circuit outputs the test mode enable signal to the device only when at least one of the control signal and the reset signal has a predetermined voltage level.
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