US Patent 7795900 Memory array with multiple-event-upset hardening

An integrated circuit has a memory array with a four-plex of SEU-hardened memory cells. Each of the SEU-hardened memory cells has an orientation different from each of the other SEU-hardened memory cells in the four-plex, and each of the SEU-hardened memory cells has a different critical ion track. Providing a four-plex of SEU-hardened memory cells, each with a different critical ion track, reduces the probability of a single ion upsetting adjacent memory cells.