Patent attributes
A synchronous memory with a shadow-cycle counter has a counter logic combiner with an address input, a registered processed-address input, an incremented-processed-address input, and a counter control input with an output that contains a processed address. A mask, counter, and mirror registers receives the processed address and has a clock input strobing around a middle of a pre-array clock cycle. An output of the mask, counter, and mirror registers forms a registered internal processed address. A clock phase shifter has a clock input and has an output coupled to the mask, counter, and mirror registers. A plane internal processed-address is coupled to the read/write control logic. An address output enable generated in the counter logic combiner is coupled to the data output enable logic.
