Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Tom W. Williams0
Cyrus Hay0
Rohit Kapur0
Date of Patent
September 14, 2010
Patent Application Number
12469820
Date Filed
May 21, 2009
Patent Primary Examiner
Patent abstract
A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.