Patent attributes
A semiconductor integrated circuit device which is improved in wiring efficiency and area efficiency. Metal layers having respective portions protruding out from an N-type diffusion layer and a P-type diffusion layer in plan view toward respective sides of the diffusion layers opposed to each other are formed over the N-type diffusion layer and the P-type diffusion layer, respectively, and contact portions are formed over the upper surfaces of the protruding portions of the metal layers such that they extend parallel to a power supply line and a ground voltage line. This produces empty spaces over the regions of the upper surfaces of the metal layers, which makes it possible to arrange a large number of conductive traces, and enhance wiring efficiency and space efficiency.
