US Patent 7801121 Serial communications systems with cyclic redundancy checking
Patent 7801121 was granted and assigned to Altera on September, 2010 by the United States Patent and Trademark Office.
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Integrated circuits such as programmable logic device integrated circuits are provided with transmitter and receiver circuitry for communicating over multi-lane serial communications links. Data is transmitted over the serial communications links in the form of data packets. Priority data packets may be nested within regular data packets. Regular data packets may be formed using start-of-packet and end-of-packet markers. The locations at which priority packets are nested within regular data packets may be denoted using suspend and continuation markers. A single cyclic redundancy check generator may be used to generate cyclic redundancy check words for the data packets. Start-of-packet markers, end-of-packet markers, suspend markers, continuation markers, and cyclic redundancy check words may be inserted and extracted from the serial communications link at fixed lane locations.
US Patent 07801121 Serial communications systems with cyclic redundancy checking US Patent 7801121 Serial communications systems with cyclic redundancy checking
US Patent 07801121 Serial communications systems with cyclic redundancy checking
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