US Patent 7802031 Method and system for high speed network application

A method and system for a PCI-Express device is provided. The PCI-Express device includes a buffer memory placed in a receive path for receiving an incoming data stream from a Fibre Channel network, wherein the buffer memory is written in a first clock domain and read in a second clock domain using at least two read pointers that are generated by a read pointer logic module, and read pointer values are adjusted based on whether a character is inserted or deleted to avoid buffer memory underflow and/or overflow conditions.