Patent attributes
Clock data recovery circuitry with a high speed level shifting circuits and methods are disclosed. One embodiment provides clock data recover with a high speed level shifting circuit that uses an input signal to generate two intermediate signals and uses the intermediate signals to generate an output signal such that voltage stress on individual devices within the level shifting circuit is minimized. In one embodiment, the level shifter includes a first driver and second driver coupled in parallel to provide intermediate signals to an output driver. In a particular aspect, individual transistors of the output driver are subject to voltage stresses that are less than the peak-to-peak amplitude of the output signal. In one embodiment, the first driver includes an n-channel metal oxide semiconductor (“NMOS”) cascode circuit, the second driver includes a p-channel metal oxide semiconductor (“PMOS”) cascode circuit, and the output driver includes a complementary metal oxide conductor (“CMOS”) inverter stage. In one embodiment, the level shifter is implemented in an integrated circuit characterized by 45-nanometer technology. In another embodiment, the level shifter is implemented in an integrated circuit characterized by 65-nanometer technology.
