Patent attributes
A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.
