Patent attributes
A buffer amplifier includes an input stage circuit, an output stage circuit and a bias circuit, providing a buffered output signal at an output terminal according to an input signal applied to a first input terminal. The input stage circuit generates four control signals in response to the input signal when the logic level of the buffered output signal is opposite to that of the input signal. The output stage circuit includes four output transistors, wherein the first and second output transistor of a first type are provided for discharge in response to a first control signal and a second control signal, and the third and fourth output transistor of a second type are provided for charge in response to a third control signal and a fourth control signal. The bias circuit is used for determining the first, second, third and fourth control signal.
