Patent attributes
A pixel structure is provided. A scan line and a data line are disposed over a substrate. A first, second, and third thin film transistors are electrically connected with the data line and the scan line. The width-to-length ratios of the second and third thin film transistors are the same but larger than that of the first thin film transistor. A first, second and third pixel electrodes are electrically connected with the first, the second and the third thin film transistors, respectively. A first, second and third common lines are disposed below the first, second and third pixel electrodes respectively. The first and second common lines are electrically connected to a first voltage and the third common line is electrically connected to a second voltage.
