US Patent 7813186 Flash memory device and programming method thereof

A flash memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including a plurality of page buffers connected to bit lines of the memory cell array, a data line mux unit connected between the page buffer unit and a data line and configured to receive verification data through a page buffer during a verify operation. The flash memory device also includes a fail bit counter unit for counting the verification data, comparing counted fail bits and the number of ECC allowed bits, and outputting a pass or fail signal of a program operation according to the comparison result.