US Patent 7814381 Semiconductor memory device

A semiconductor memory device is adapted so that access time can be measured accurately when the device is in a test mode. A read or write operation of a memory array in the normal mode is performed in accordance with a first signal, a read or write operation of the memory array in the test mode is performed in accordance with a second signal, and a test of a plurality of items of output data from the memory array is conducted in the test mode and results of the test are output. It is so arranged that a desired test is conducted in the test mode based upon a third signal unrelated to the first signal and second signal.