Patent attributes
The semiconductor device of the present invention has a body layer of a P-type impurity region formed on an N− layer of an N-type impurity region. A plurality of trenches is formed through the body layer from the main surface thereof. A gate insulating film and a gate electrode are formed in each trench. A contact layer of a P-type impurity region and an emitter layer of an N-type impurity region are formed on the main surface of the body layer. A plurality of floating ring layers of P-type impurity regions is formed on the main surface of the N− layer, being spaced apart from the body layer. A well layer of an N-type impurity region is formed between the body layer and N− layer in an area contained in the body layer in plane view.