US Patent 7818509 Combined response cancellation for load command
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Patent abstract
A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption.
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Patent Inventor Names
Brian Mitchell Bass0
Eric Francis Robinson0
Thuong Quang Truong0
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Official Website
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US Patent 07818509 Combined response cancellation for load command US Patent 7818509 Combined response cancellation for load command
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Patent Number
078185090
Patent Number
78185090
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Patent Jurisdiction
Patent Number
078185090
Date of Patent
October 19, 2010
0Patent Application Number
119303930
Date Filed
October 31, 2007
0Official Website
Patent Primary Examiner
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US Patent 07818509 Combined response cancellation for load command
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Is a
Patent jurisdiction
Patent number
07818509
Date of patent
October 19, 2010
Patent application number
11930393
Date Filed
October 31, 2007
Patent primary examiner
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