US Patent 7823001 Latency adjustment between integrated circuit chips
Patent 7823001 was granted and assigned to Mentor Graphics on October, 2010 by the United States Patent and Trademark Office.
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Patent abstract
In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.
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US Patent 07823001 Latency adjustment between integrated circuit chips US Patent 7823001 Latency adjustment between integrated circuit chips
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Patent Number
0782300100
Patent Number
782300100
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Official Website
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Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
078230010
Date of Patent
October 26, 2010
0Patent Application Number
115535320
Date Filed
October 27, 2006
0Official Website
Patent Primary Examiner
Edits on 6 Oct, 2022
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Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
078230010
Date of Patent
October 26, 2010
0Patent Application Number
115535320
Date Filed
October 27, 2006
0Official Website
Patent Primary Examiner
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US Patent 07823001 Latency adjustment between integrated circuit chips
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07823001
Date of patent
October 26, 2010
Patent application number
11553532
Date Filed
October 27, 2006
Patent primary examiner
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