US Patent 7823159 Intelligent memory device clock distribution architecture

A computing system that includes one or more processing elements, a memory connected to a host processor and a multitask controller, where the multitask controller includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The processing elements, the scheduler unit, the data flow unit, the executive unit, and the resource manager unit are each synchronously clocked by a clock signal. The processing elements, multitask controller interface of the memory, the executive unit, and the scheduler unit are each operative to change one or more interface signals on a positive transition of the clock signal while the resource manager unit and dataflow unit are each operative to change one or more interface signals on a negative transition of the clock signal. Because adjacent units are clocked on opposite edges, the speed of transfer of information between the units is improved.