US Patent 7825524 QFN housing having optimized connecting surface geometry

A semiconductor system or sensor system in a housing which is butt-joined to a printed circuit board by soldering, at least some of the connecting surfaces not being soldered over their entire area, the connecting surfaces which are not soldered over their entire area being fixedly soldered in a first surface region to a section of a printed conductor, and in a second surface region the connecting surfaces not being fixedly connected to the printed circuit board, the securely soldered surface regions being situated closer to the semiconductor or sensor structure to be contacted than are the surface regions which are not fixedly connected to the printed circuit board.