Patent attributes
In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.
