US Patent 7835465 ADC architecture for wireless applications

A simplified architecture is disclosed for use in wireless receiver applications, particularly for ADC conversion of received in-phase I and quadrature Q signals. Circuit area is substantially reduced by sharing a single ADC to convert both signals, switching the ADC input alternately between the i and q signals. In an embodiment, the ADC is clocked at an increased sample rate, and the digital output signals are aligned to compensate for the phase difference resulting from the implementation of a single ADC.