US Patent 7836380 Destination indication to aid in posted write buffer loading

Embodiments of the invention are generally directed to systems, methods, and apparatuses for a destination indication to aid in posted write buffer loading. In some embodiments, a memory device includes a posted write buffer having a first element and a second element. The memory device may also include logic to detect a destination indication associated with received write data. In some embodiments, the logic determines whether to store the received write data in the first element or the second element based, at least in part, on the destination indication. Other embodiments are described and claimed.