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US Patent 7840842 Method for debugging reconfigurable architectures

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Patent Citations Received
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US Patent 12132699 In-line transmission control protocol processing engine using a systolic array
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US Patent 11803507 Data stream protocol field decoding by a systolic array
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Patent abstract

A method is described for debugging reconfigurable hardware. In one example embodiment, debugging information is written for each configuration cycle into a memory which is then evaluated by a debugger.

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Patent Inventor Names
Armin Nückel0
Frank May0
Martin Vorbach0
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US Patent 07840842 Method for debugging reconfigurable architectures US Patent 7840842 Method for debugging reconfigurable architectures

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Patent Number
078408420
Patent Number
78408420
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=078408420
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Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
078408420
Date of Patent
November 23, 2010
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Patent Application Number
118900940
Date Filed
August 3, 2007
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=078408420
Patent Primary Examiner
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Dieu-Minh Le
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=07840842
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 US Patent 07840842 Method for debugging reconfigurable architectures

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
07840842
Date of patent
November 23, 2010
Patent application number
11890094
Date Filed
August 3, 2007
Patent primary examiner
‌
Dieu-Minh Le

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