US Patent 7840922 Semiconductor design support apparatus

The semiconductor design support apparatus relating to the layout verification. For executing layout verification in high accuracy, the apparatus includes a unit for generating a recognition pattern in a region having a first axis of symmetry and a second axis of symmetry orthogonal to the first axis. The recognition pattern is asymmetric to both first and second axes. The layout execution unit determines the layout of a macrocell including the recognition pattern to generate layout pattern data. The layout verification unit read the pattern data of the recognition pattern included in the macrocell based on the layout pattern data and verify the arrangement direction of the macrocell based on the recognition pattern.