Patent attributes
Information of a logic circuit including a hierarchical structure and connection target information up to a connection target including a pin or a net via hierarchies of the logic circuit are read, and a tree structure in which a hierarchy is taken as a node and a connection target is taken as a leaf is produced. The tree structure is referred from its root, and a node from which the tree branches is set to an uppermost node. A leaf the connection target of which is a net is searched from the tree structure, and a hierarchy port or a net in a lower hierarchy is added as a leaf to a lower hierarchy node connected with a net via a hierarchy port. Connection processing is performed to the tree structure from bottom up and the information on the logic circuit is rewritten, and the logic circuit information is outputted.