US Patent 7842558 Masking process for simultaneously patterning separate regions
Patent 7842558 was granted and assigned to Micron Technology on November, 2010 by the United States Patent and Trademark Office.
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According to another embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.
US Patent 07842558 Masking process for simultaneously patterning separate regions US Patent 7842558 Masking process for simultaneously patterning separate regions
US Patent 07842558 Masking process for simultaneously patterning separate regions
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