US Patent 7843762 RAM control device and memory device using the same

In a RAM control device, an arbiter circuit is means for generating BUSY1 and BUSY2 of exclusive logic with CLK1 and CLK2 so as to give a right to access RAM3 to a host which has transmitted the first access clock and requesting a one-shot circuit to generate RAMCLK for deciding the timing to access the RAM3. The one-shot circuit is means for generating one pulse of RAMCLK with CLKRQ from the arbiter circuit and transmitting it to the RAM3. This configuration suppresses increase of the device size and cost and enables appropriate control of access to the RAM according to the access clocks of two systems inputted asynchronously.