US Patent 7846815 Eutectic flow containment in a semiconductor fabrication process
Patent 7846815 was granted and assigned to Freescale Semiconductor on December, 2010 by the United States Patent and Trademark Office.
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A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure.
US Patent 07846815 Eutectic flow containment in a semiconductor fabrication process US Patent 7846815 Eutectic flow containment in a semiconductor fabrication process
US Patent 07846815 Eutectic flow containment in a semiconductor fabrication process
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