Patent attributes
A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.
