US Patent 7848130 Method and apparatus for improving SRAM write operations

A memory cell includes an access transistor, first and second pull-up transistors, first and second pull-down transistors, and a first search transistor. The access transistor is connected to a first word line and connected between a first bit line and a first data node. The first pull-up transistor is connected to a first power supply point and the first data node, and the second pull-up transistor is connected to the first power supply point and the second data node. The first pull-down transistor is connected to a second power supply point and the first data node, and the second pull-down transistor is connected to the second power supply point and the second data node. The first search transistor is connected to the second data node and includes a source terminal connected to a third power supply point comprising a voltage less than the voltage at the second power supply point.