US Patent 7851848 Cylindrical channel charge trapping devices with effectively high coupling ratios

A memory cell comprising: a source region and a drain region separated by a semiconductor channel region, the channel region having a channel surface having an area A1 including a first cylindrical region, a first dielectric structure on the channel surface, a dielectric charge trapping structure on the first dielectric structure, a second dielectric structure on the dielectric charge trapping structure, a conductive layer having a conductor surface having an area A2 including a second cylindrical region on the second dielectric structure, the conductor surface overlying the dielectric charge trapping structure and the channel surface of the channel region, and the ratio of the area A2 to the area A1 being greater than or equal to 1.2 are described along with devices thereof and methods for manufacturing.