US Patent 7852690 Multi-chip package for a flash memory

An electronic system includes a flash memory die having multiple flash memory cells. Each flash memory cell is operable to store at least four bits of data. A second die includes a controller for accessing the flash memory cells. DRAM is used by the controller to temporarily store data. An interface is operable to send and receive signals associated with the flash memory cells to a host. A housing contains the flash memory die, the second die, the DRAM, and the interface.