Patent attributes
Sense logic, and associated signaling, for dynamic thyristor-based memory cells is described. A first supply voltage level is greater than a second supply voltage level. In an embodiment, cross-coupled inverters of a sense amplifier are operatively coupled between a ground node and the second supply for sensing voltage. The first supply voltage is pass gate coupled to a first sense node and a second sense node. The pass gating is responsive to sample signaling. A first supply transistor is gated by a transfer bus. A second supply transistor is gated by a sense reference voltage that is between the first supply voltage level and the second supply voltage level. Each of the first supply transistor and the second supply transistor is back body biased with a write voltage level that is between the second supply voltage level and the ground voltage level.
