Patent attributes
A dithering system includes a linear transformer, a dither data generator, an adder and a shifter. The transformer linearly transforms M bit input data using a linear function having a predetermined gradient in order to generate and output M bit transform data. The dither data generator generates and outputs M−N bit dither data. The adder adds the M bit transform data and the M−N bit dither data to generate and output M bit correction data. The shifter cuts off the bottom M−N bits of the M bit correction data in order to generate and output the N bit output data. The dithering system and associated dithering method widely disperses an error generated due to a physical limit of a data bit that can be expressed by a low gray scale system throughout the entirety of the gray scales when high gray scale image data is converted to low gray scale image data. This is done without using a lookup table which avoids using valuable chip area. In addition, by utilizing a plurality of adders and shifters rather than a multiplier and divider, the number of required logic gates is remarkably reduced as well as reducing associated power requirements.
