US Patent 7864620 Partially reconfigurable memory cell arrays

Partial reconfiguration techniques and reconfiguration circuitry are provided that allow portions of a memory cell array to be reconfigured with new reconfiguration data without disturbing other portions of the memory cell array. The memory cells may be loaded with configuration data on an integrated circuit such as a programmable logic device. Memory cell outputs may configure programmable logic. To avoid disturbing programmable logic operations for programmable logic that is unaffected by the reconfigured cells during reconfiguration, unaffected memory cells are not unnecessarily cleared. Only those memory cells that need to be cleared to conform to the new configuration data that is being loaded into the array need to be loaded with logic zero values during reconfiguration operations. After these clearing operations are complete, set operations may be performed to convert appropriate memory cells to logic one values to match the new configuration data.