US Patent 7864816 Integrated circuit for network delay and jitter testing

An integrated circuit having a corresponding method comprises one or more ports to transmit and receive packets of first data; and a forwarding engine to transfer the packets of the first data between the ports; wherein at least one of the ports comprises a packet generator to originate a first packet of the first data comprising second data representing a time of transmission of the first packet of the first data, a network transmit interface to transmit the first packet of the first data, and a network receive interface to receive a second packet of the first data transmitted in reply to the first packet of the first data; and a controller to calculate a network delay based on the second data representing the time of transmission of the first packet of the first data and the second packet of the first data.