US Patent 7865635 Buffer device, buffer arrangement method, and information processing apparatus

A buffer device that transfers data and is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each CPU core breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, includes a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein the line buffers are paired into line buffer groups, and the line buffers in each buffer group are arranged symmetrically about the reference line.