Patent attributes
In a synchronous semiconductor device (250), an input/output control circuit is formed of a clock input I/O (260), a clock control signal input I/O (270) and a signal change detection circuit (280). The clock input I/O (260) includes a first input buffer (264) having a large threshold, a second input buffer (266) having a small threshold and an input selector (268). The signal change detection circuit (280) controls the input selector (268) so that a first input from the first input buffer (264) is normally selected and a second input from the second input buffer (266) is temporarily selected only when the signal change detection circuit (280) detects that a logic level of a clock control signal (279) is changed from a non-activated level to an activated level.
