US Patent 7869275 Memory structure capable of bit-wise write or overwrite

An integrated circuit includes a plurality of tiles. One tile is a master tile. Other tiles contain writable registers of memory structures. Information for configuring circuitry of the tile is stored in the register in the tile. An individual one of the registers can be written via the master tile. Each memory structure of a register includes a non-volatile floating gate cell (that stores the configuration information) as well as a volatile cell. All transistors have the same gate insulator thickness. Although a programming pulse signal is applied to all memory structures, the state of the non-volatile cell of a memory structure is only changed if the state stored by the associated non-volatile cell differs from the state stored by the volatile cell. Floating gates are automatically refreshed by the programming pulse signal. By storing configuration information in each tile, inefficiencies associated with using blocks of non-volatile memory are avoided.