US Patent 7870448 In system diagnostics through scan matrix

A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is tested, the integrated circuit chip comprises a scan matrix controller and an instruction register. The scan matrix controller is provided for partitioning said circuitry into multiple matrices, each of the matrices having a plurality of scan elements. The instruction register is provided for holding instructions for the scan matrix controller for partitioning the chip into said multiple matrices. The scan matrix controller is further arranged to test each of said matrices according to instructions in the instruction register by applying a test signal to the tested part of the circuitry.