Patent attributes
A testing circuit has a shift register circuit (76) for storing instruction data for the testing of an integrated circuit core. Each stage of the shift register circuit comprises a first shift register storage element (32) for storing a signal received from a serial input (wsi) and providing it to a serial output (wso) in a scan chain mode of operation, and a second parallel register storage element (38) for storing a signal from the first shift register storage element and providing it to a parallel output in an update mode of operation. The testing circuit further comprises a multiplexer (70) for routing either a serial test input to the serial input (wsi) of the shift register circuit or an additional input (wpi[n]) into the serial input of the shift register circuit (76). In a preferred example, the testing circuit further comprises a control circuit (78) which responds to a specific value of data stored in at least one stage of the shift register to generate an update signal for setting the other shift register stages into the update mode of operation.
