US Patent 7872463 Current balance arrangement

A current mirror arrangement comprising two transistors (11, 12) which are of different conductivity types and are each suitable for outputting a bias current (PBIAS, NBIAS) is specified. A controlled current source (13, 13′) is connected between the two transistors (11, 12) and forms the output of a current mirror (18, 13′). The proposed principle ensures that the output bias signals (PBIAS, NBIAS) match one another in a highly precise manner. The proposed current mirror arrangement may preferably be integrated using CMOS circuit technology.