Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Sehat Sutardja0
Jody Greenberg0
Date of Patent
January 18, 2011
0Patent Application Number
121808530
Date Filed
July 28, 2008
0Patent Primary Examiner
Patent abstract
An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A tunable circuit having variable capacitance is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.
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