Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Joerg Volrath0
Marcin Gnat0
Date of Patent
January 18, 2011
Patent Application Number
12193267
Date Filed
August 18, 2008
Patent Primary Examiner
Patent abstract
An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is positioned in a second plane that is different than the first plane. The second plurality of bit lines is electrically coupled to a second set of the memory cells.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.
