Patent attributes
A current limiting circuit, especially for an RF power amplifier (PA) having a power control loop. The circuit is adapted to sense a representation of a bias current fed to a final stage of the PA. The sensed representation of the bias current is compared to a predetermined reference current and a signal is fed back to the power control loop upon the sensed representation of the bias current exceeding the reference current so as to limit output current of the PA. This provides a limitation of a current drawn by the PA which is generally insensitive to supply voltage and temperature variations. Optionally, a second circuit may be added to limit current drawn by the PA. The second circuit comprising a high accuracy VI converter that is adapted to compare a voltage VLIM representing a feed-back voltage of the power control loop and a predetermined reference voltage VBGAP. The circuit is operatively connected to the VI converter so as to reduce the output current lout upon the voltage VLIM representing the feed-back voltage exceeding the predetermined reference voltage VBGAP. Under antenna mismatch conditions both circuits help to limit a supply current drawn by the PA compared to prior art power control loops that are unable to detect and limit a high current draw under mismatch conditions.