Patent attributes
A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, performing a stress test of the functional element while the functional element is in the idle cycle, and indicating that the functional element, if it fails the stress test, is a potential future failing element. The stress test can include simultaneously providing a margining test voltage and a stress clock signal to the functional element. The stress test is performed in the background, during continuous operation of the integrated circuit device, such that normal operation of the integrated circuit device is not interrupted. Thereby, the method and apparatus of the present invention allows for failure prediction in a device before it happens, allowing for planned outages or workarounds and avoiding system downtime for unplanned repairs.
