Patent attributes
A semiconductor memory device includes a delay locked loop to generate a delay control signal corresponding to a detected phase difference between reference and feedback clock signals, a delay locked loop (DLL) clock signal, and the feedback clock signal. The memory device further includes a delay time measurement device to measure a first degree of delay between the reference and feedback clock signals and output a delay measurement value, and an output enable signal generation device to delay read command information synchronized with an external clock signal by a second degree of delay between the reference and DLL clock signals. The output enable signal generation device generates the read command information as final output enable signal by synchronizing the read command information with the DLL clock signal according to the delay measurement value and column address strobe (CAS) latency information.
