Patent attributes
A power consumption analyzing method, to be implemented by a computer, is for a circuit developing procedure that makes a logic design of the circuit in an RTL design stage and inserts a gated clock with respect to the circuit in a subsequent logic synthesis stage. The method comprises an extraction step, implemented by the computer, extracting a signal which is judged that it will be transformed into a gated clock in the logic synthesis stage, and storing the signal in a memory part, a measuring step, implemented by the computer, measuring an valid time of the signal stored in the memory part by a logic simulation, and storing the valid time in the memory part, and a post-simulation step, implemented by the computer, computing a power consumption analysis result of the circuit from the valid time stored in the memory part, a number of registers for each of modules that are function units forming the circuit, and a memory capacity coefficient indicating an extent to which a memory capacity within the circuit affects the power consumption of the circuit, and outputting the power consumption analysis result.
