US Patent 7882460 Method of circuit power tuning through post-process flattening

A method is provided for optimizing a hierarchical circuit design containing at least one reused cell. A first optimization is performed on the circuit design to meet a first objective. The first optimization is subject to a first constraint that all instances of the at least one reused cell are kept identical. The at least one reused cell is uniquified. A second optimization is performed to meet a second objective allowing uniquified instances of the at least one reused cell to be independently modified. The second optimization is subject to a second constraint that the first objective remains met.