US Patent 7884016 Liner materials and related processes for 3-D integration

In some embodiments, a low-k dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of through-silicon vias used in three-dimensional (3-D) integration of integrated circuits. A semiconductor workpiece having a via is provided. A dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of the via by chemical vapor deposition. Following the deposition of the dielectric film liner, conductive material is deposited into the via. The conductive material on the bottom of the via can be exposed by thinning the back of the semiconductor workpiece, thereby forming a through-silicon via. The semiconductor workpiece can form a stack with one or more additional semiconductor workpieces having vias filled with conductive material to form a 3-D integrated circuit. The conductive material electrically interconnects the integrated circuits at different levels of the stack.