US Patent 7884674 Clock and data recovery circuit

An embodiment of the invention provides a clock and data recovery circuit. The clock and data recovery circuit comprises a phase detector, a pre-accumulator, a register, an accumulator and a digital controlled oscillator. By using the transmission path formed by the pre-accumulator, the output of the phase detector can be transmitted to the digital controlled oscillator in advance to adjust the frequency of its output clock signal and the latency due to the accumulator can be reduced.